1. Field of the Invention
This invention relates to semiconductor memories, particularly to non-volatile memories using variable threshold transistors.
2. Description of the Prior Art
In certain non-volatile memory applications it is desirable to have a short write cycle time to enable fast writing into the memory as well as reading out. One application suitable for a high speed write cycle memory is a scratch pad memory used for temporary storage of data in a computer. Memories utilizing variable threshold devices such as metal nitride oxide semiconductor (MNOS) transistors have been previously described such as in U.S. Pat. No. 3,836,894 which was issued on Sept. 17, 1974, entitled "MNOS/SOS Random Access Memory," invented by the inventor herein and assigned to the assignee herein. Information or data in a memory cell of a typical prior art MNOS memory was cleared or written to a low threshold or binary one state first regardless of the data in the memory cell. Secondly, selected memory cells were written to the high threshold or binary zero level. The write cycle for writing ones and then zeros into a memory cell is more than twice the minimum write pulse width.
In an MNOS memory of the prior art, data may be rewritten into the memory over and over. In other words, the memory cell may be written as a binary one for a number of times in a row before a binary zero is written. This causes the variable threshold transistor to shift its threshold to the maximum extent under the writing conditions called the saturated threshold state. When it is desired to write a binary level of the opposite state into the memory cell, the single write pulse must have adequate polarizing voltage and time to shift the threshold voltage of the transistor from the previous saturated state, for example minus 2 volts, to an opposite unsaturated state such as minus 5 volts. The typical write duration time to shift the threshold of an MNOS transistor from a saturated state representative of a first binary level to the second binary level for example 3 volts, is typically 2 to 3 microseconds. This means the minimum write cycle time for a MNOS memory of the prior art is limited to 4 to 6 microseconds.
In order to speed up the time of writing a binary level or shifting the voltage in a variable threshold transistor such as an MNOS transistor, the voltage or electric field across the gate insulator is increased by increasing the polarization voltage. Unfortunately, high electric fields across the gate insulator of a variable threshold device during the write cycle accelerates the undesirable endurance phenomena such as a smaller threshold voltage window and decreased retention time. The endurance phenomena of MNOS transistors runs counter to the requirement for a memory transistor that can withstand a large number of write cycles in typical random access memory applications.
In copending application Ser. No. 700,235, filed June 28, 1976 (W. E. Case 46,472), there is described a dual-mode memory system wherein the threshold of a dual gate MNOS memory transistor may be sensed by comparing the conductivity of a memory transistor in an array with the conductivity of a reference transistor. Alternately the memory transistor may be sensed by comparing the conductivity of the memory transistor in an array of transistors with the conductivity of another memory transistor in the array for each transistor. In place of comparing the conductivities of the memory transistors, the threshold voltages may be compared.
It is therefore desirable to have a variable threshold transistor memory which eliminates the clear or write cycle now required to write binary ones before writing zeros in selected memory cells. This would allow the shortest write cycle time since the data would be written into the memory cell directly during one write cycle.
It is furthermore desirable to minimize the number of write cycles experienced by the memory cells when the memory cells are utilized as a scratch pad memory to reduce the exposure of high electric fields to the gate insulator of the variable threshold transistors to retard the onset of endurance phenomena.
It is furthermore desirable to limit rewriting of the same data into the same memory cell over and over which drives the variable threshold device into threshold saturation.